1. Field of the Invention
The invention relates in general to the field of logic circuits, and, more particularly, to logic circuits used in computer systems. Specifically, the invention relates to an input buffer to interface between a central processing unit and other components on a main logic circuit within a mixed voltage environment.
2. Description of the Related Art
With the growing complexity of modern computer systems and the availability of various types of peripheral devices on the main circuit board, designers are constantly seeking more efficient methods to improve the circuits that serve as interfaces between these peripheral devices and the central processing unit.
Typically, a voltage V.sub.cc is associated with a processor voltage supply, while a voltage V.sub.ccp is associated with a peripheral voltage supply. The peripheral voltage Vccp is often larger than the processor supply voltage. The voltage differences between these two voltage levels often warrant an interface circuit within the processor to be positioned between the core of the processor and other external components.
Designers today often utilize advanced processors in which the processor supply voltage level has been lowered quickly because of technological advances, while the peripheral supply voltage is level has been reduced more slowly. This behavior may cause the voltage difference between the peripheral supply voltage and the processor supply voltage to further increase. Transistors generally have a maximum voltage difference V.sub.MAXd that can be applied between the enable terminal and either one of the other terminals. When this voltage difference is exceeded, the transistor may become damaged or fail to operate properly. Gate stress generally results when a voltage difference beyond the maximum voltage difference V.sub.MAXd is applied to the enable terminal of a transistor. One skilled in the art will appreciate that the voltage difference V.sub.Maxd is typically a little more than the voltage V.sub.cc, though lower than the voltage V.sub.ccp. This characteristic of the voltage difference hinders the input signals from being applied directly to internal transistors within the central processing unit.
To reduce the likelihood of damaging a microprocessor (i.e., central processing unit), signals that are generated by a peripheral device and are to be sent to the microprocessor are generally first sent to an input buffer before being sent to other locations within the processor. The input buffer generally receives the input signal and generates a corresponding signal with a voltage level within an allowed range. The input buffer may also be designed to improve the quality of the input signal by removing some of the distortion such that the signals may be used more effectively.
FIG. 1 is a circuit diagram for a conventional input buffer 100 in which an input signal from a peripheral device is applied to a line 105. The input buffer 100 generates an output signal corresponding to the input signal, which is applied to a line 110 and sent to other logic devices inside the processor. A transistor 120 has a gate (enable) terminal 122 coupled to a reference voltage supply, which generates a logically high voltage equal to the voltage V.sub.cc. When a logically high voltage is applied to the gate terminal 122, the transistor 120 conducts, allowing the input signal applied to the line 105 to be applied to a line 124.
If a high signal is applied to the line 105, the transistor 120 reduces the voltage of the signal passed to the line 124 to approximately the voltage V.sub.cc -V.sub.tn. As previously mentioned, the reference voltage from a peripheral power supply is generally considerably higher than the reference voltage from processor power supply. The voltage level of the logically high input signal is referenced to the voltage V.sub.ccp and may vary slightly above or below that voltage. By sending the input signal through the transistor 120, the voltage level of the signal is reduced considerably to the voltage V.sub.cc -V.sub.tn.
By reducing the voltage level of the signal on the line 124, the transistors 130, 135 are not subjected to gate stress. In addition, the transistor 120 is protected from gate stress because the gate terminal is connected to voltage V.sub.cc constantly. One skilled in the art will appreciate, if the transistor 120 was removed, the transistors 130, 135 may suffer from gate stress. In addition, the transistors 130, 135; 140, 145 are configured to function as an inverter. Thus, the logic state of the signal on the line 110 would be same as the logic state of the signal on the line 105. A transistor 150 may be used to pull the line 124 to the voltage V.sub.cc instead of remaining at the voltage V.sub.cc -V.sub.tn.
One skilled in the art will appreciate that the input buffer 100 simply passes any logically low signals applied to the line 105 without affecting their voltage level. The input buffer 100 functions to reduce the peripheral voltage level on the line 124 in such a manner as to reduce the probability of causing gate stress on the transistors 130, 135 in the first inverting stage. When the core reference voltage V.sub.cc is lowered, the voltage level of the signal applied to the line 124 is reduced. One skilled in the art will appreciate that this voltage reduction may be desired in advanced processors. The voltage level generally needed to activate (i.e., trip) the inverting stages, consisting of the transistors 130-145, is approximately equal to the voltage 1/2V.sub.cc.
By reducing the voltage level on the line 124, the inverting stages may malfunction because the voltage on the line may be sufficiently close to the trip voltage. Although the input signal reaches the voltage V.sub.ccp, the NMOS pass gate 120 passes only the voltage V.sub.cc -V.sub.tn. This voltage may not be sufficient to switch the first inverting stage of the input buffer, since the voltage V.sub.cc -V.sub.tn is often not larger than the trip voltage of the first inverting stage, which includes the transistors 130, 135, when the voltage V.sub.cc is reduced. Alternatively, the first inverting stage may switch at a considerably slower rate. Thus, the conventional input buffer 100 is sensitive to the value of the core reference voltage V.sub.cc. It would be beneficial to have an input buffer that is capable of overcoming the shortcomings of conventional input buffers.
Another disadvantage of the input buffer 100 occurs when the maximum low voltage input signal is not equal to a voltage V.sub.ss, and instead is equal to a voltage very close to the an industry standard voltage of 0.7 volts. In this case, the first inverting stage (i.e., the transistors 130, 135) would fail to switch because it would not recognize the voltage level of the signal on the line 124 as a logic zero. In addition, the use of core voltage supply for the first inverting stage of the input buffer limits the input buffer's maximum input low value as the voltage V.sub.cc is reduced. When the voltage V.sub.cc is reduced, trip point is reduced accordingly, which inhibits recognition of low voltages. The reduction of the trip point generally leaves a small noise margin, causing the probability of false logic to increase. Thus, it would be beneficial to have an input buffer that is capable of overcoming the shortcomings of conventional input buffers.